While the Image Mode will preserve colors, the paint modes pigment selections will be limited to just After this decision, we have need for 4 SRAM inputs, 4 SRAM outputs, and 5 joystick inputs for four directions and a button , but only nine pins exist to fit these.
This allows the joystick button and the outputs to write to SRAM to receive their own un-shared or un-multiplexed pins, unperturbed. The final choice came to distribution of the pin assignments. We then wanted to put the five input pins alongside other bits that could be changed in isolation without altering them all at once since we should not be reassigning port values for the input bits, so as to enable pull-up resistors and potentially alter our circuit conditions; meanwhile, other operations to affect a cluster of bits in a single port but not others will be more costly in terms of time, which is disadvantageous to us in this project.
Thus, the input pins were matched alongside the Horizontal and Vertical sync in addition to the Tri-state output enable—each of which is assigned as an individual bit and independently of the others—on PORTD.
Next, we need to assess the timing of our operation. Although we generally use a 16 MHz crystal in lab, Now, we can observe how this will impact our capacity for output, knowing that we will follow the general VGA standard and spend cycles processing each line at the proper frequency, and use this to identify an optimal number of lines to process to match a standard 60 Hz refresh rate as closely as possible.
For convenience, we decided to have lines per screen, and can proceed to identify the following. The most critical feature of VGA is precise and consistent timing. We observed from various examples that a single clock cycle difference between horizontal screen lines of output results in a jagged, zigzag appearance since one clock cycle difference equates to a one pixel shift.
Since each clock cycle represents a pixel, this indicates that the only way to obtain full resolution across a line is to change the output for every pixel, and thus, every clock cycle. With this in mind, we proceeded to implement the body of our code in assembly language. Even with the body in assembly, we were left to consider different design implementations as to how to output VGA signal to the screen.
Two ideas were having the assembly body output a single line to the screen versus having the assembly body output an entire screen. In the interests of pushing the capacity of the MCU as far as possible, we began testing concept [1] just to see if it would work. We could observe that the output was consistent and the interrupt was being called in equal intervals in trials with a prescaler of However, as the prescaler was lowered to approach the realistic and required value of one, we noticed significant performance degradation and lag time on interrupt calls, eliminating this from our list of viable solutions.
We proceeded to investigate naked interrupts for concept [2], and began conducting trials with those but noticed performance degradation here, as well, although it took longer to reach lag here than in the previous case, but it still occurred before reaching a prescaler of one. Between remaining concepts [3] and [4], we decided in the interests of granular control to pursue concept [4] since we would consistently be fully cognizant of the number of clock cycles for performance and could use that insight to keep our options open for project extensions and a larger pool of potential applications to display on the VGA later in the process once image display was successfully achieved.
Schematics of the displayed circuity available in the Appendix. The necessary considerations for the selection of the hardware were driven by the need to execute tasks that the microprocessor that we had the most familiarity with [the Atmel MEGA ] is not particularly suited for the task of driving video. We saw this as a primary challenge to the project and set about initially to improve upon other examples in terms of screen resolution and execution features.
The initial hardware platform was inspired through a reference project where someone attempted to build a VGA driver using the The basic platform was adapted to our needs and then added ot as necessary to confront the hacks others used to overcome the system limitations.
The basic task is to write pixels to a screen. Considering the VGA standard of x active pixels, this yields over , pixels sent to the screen 60 times per second. Each pixel can be represented as a byte to yield a color palette, and this in turn, generates 2. Therefore some serious outboard memory will be required.
Additionally, the flow control of this data stream needs to be tightly controlled and data bus collisions must be avoided for this to work. Therefore, a traffic cop is needed to enforce blanking intervals to ensure proper synchronization and to allow for writing information to the outboard memory as well as reading the stored memory to send it to the screen.
The last component of the core hardware is a DAC to interpret the color palette we have sent to the screen and generate the analog R-G-B information that the VGA monitor is waiting for.
The choices of the hardware reflect the concept that we will be dealing with the data a byte at a time and do not need bit-accurate recall; one command reads, writes or passes through a byte colored pixel in one motion. Given that the response time of the SRAM is on the order of 10 nS, this will be quick enough to work; older hardware such as the eeprom chips kicking around our shop have both insufficient capacity and their access times were too long by at least an order of magnitude.
The real difficulty in the SRAM concept was the package. Chips of the capacity and speed to fit our needs are not available in a PDIP format. It seems that a pin adapter either does not exist or is sufficiently rare as to avoid detection. Next, the logic gate array that will interface with the processor was built using standard LS-series logic linear circuits; these are industry standard and even if our processing time is fast, the switching characteristics of these common chips are generally fast enough: on the order of nS.
The last selection was to be that which drove the entire project: the timing crystal. Overclocking results in higher power draw, higher operating temperatures, and the possibility of processor breakdown through timer errors or the inability of outport ports to cycle fast enough.
Obviously, we took the overclock route and selected a Power was supplied by a standard style voltage regulator, a T5. This supplies a regulated 5VDC supply at 1. The circuits were assembled on spare solderboards found in the MAE and ECE labs that had friendly configurations and were populated by hand. Signal flow is generally not as one would expect, that is that the MCU would access the byte stored in memory and send it to the screen. Not only could the processor run fast enough to accomplish this, but there is no real need to do so.
Rather, the MCU sends a stream of addresses to the SRAM, which then dumps the needed byte directly to the tristate to be exported to the screen. In the Paint Mode, the image needs to be updated by some method and then sent to the screen, thus requiring the additional steps of updating the pixel information and writing the byte to the SRAM so that it may be sent to the screen in the future. The block diagram would look the same; the MCU would simply add the process of repeatedly iterating the write process as well as the read process of the SRAM.
This would affect an animation or a trace being drawn across the screen, for example. If a user interface is desired, then the flow is more complex with the selection of enabling the signal from the user such as a joystick when there is no signal being sent to the screen.
We could have done this through a separate pinout from the MCU, unfortunately, the ports are fully populated and so we required a passive method of doing this. The logic gates are also buffered by the TriState 2, as previously mentioned. If this was not done and simple And gates were used, then when the user signal was disallowed the output would be driven to a logical low and data collisions would occur.
Moreover, by using a truth-table style approach to scheduling of user interface we were able to exploit those valuable times when the processor was not parsing data to the screen to interact with the user or to process the image itself. Our final hardware architecture evolved into something quite different than what it started as due to the limitations of the microprocessor and the desire for enhanced functionality.
In order for us to be able to implement a paint-style application it became necessary to create additional functionality independent of the MEGA Additionally, we used a set of manual jumpers and multipin headers to switch between operational modes. We were simply out of Pins on the to access all the addresses any other way. Likewise, Jumper J2 selects or deselects the logic set depending on which operating mode you are using, much like any number of computer components such as hard drives.
This low-tech solution to a high-tech limitation is a great way to leverage your resources when needed. One of the component functionalities of our product allows users to display their own image on the VGA monitor.
For each rectangle in the prospective newly-resolved image, the program reviews all pixels in the input image that lie within that rectangular space and collect their RGB values. Then, it will compute Red, Green, and Blue values for the rectangle by summing the Red, Green, and Blue values of the pixels in the input image that lie within that rectangular space, weighting each value by the fractional area the given pixel inhabits in the area of the whole rectangle whose RGB is being identified.
For our 8-bit colors, we assign two bits for Red, two bits for Blue, two bits for Green, and two bits for Shading which makes the displayed color brighter or more white-based, which we will return to later.
Thus, we needed to map the domain of 0 to to the range of 0 to 3 for each color. For the entirety of the domain 0 to , the goal is to identify a function that has each of the output values 0 to 3 evenly represented. We do this keeping in mind that for the paint mode of the application, values will re-be colorized from 8-bit to 4-bit; since the most significant bit of each color element RGBS will be used independently for that conversion, we want to ensure that having the color asserted or not asserted happens for an equal range of our 8-bit or the standard original image's 8-byte input domain.
For this, we can right-shift the RGB values by six to reduce the initial 8-bit value to a 2-bit one, also maintaining evenness of domain distribution across the range. Finally, we calculate the shading—with higher shading values indicative of more brightness.
For this, we surveyed 8-byte colors to qualitatively observe trends that dictate noticeable brightness changes. Namely, we saw that increasing the Red, Green, or Blue in isolation with the others set to zero results in—obviously—increasing the presence of the color, but lacks a noticeable change in brightness, even when the changing color has been adjusted to As such, the mapping function that we use to determine the two shading bits from RGB will likely not include R, G, or B values by themselves in a sum.
Rather, increasing a pairwise combination of Red, Green, or Blue results in noticeable brightness changes. Thus, we can calculate a shading score as follows, where WA stands for the weighted average from above, and x represents the position of a pixel in our newly-resolved image:. We continue using the weighted averages since they offer more control over granularity for our calculations.
We selected , , and as those points, and solved the above equation for Shading with those as input parameters. Thus, if a given pixel in the newly-resolved image maps to a Shading x below that of the first threshold , shading is zero. For values above 's shading but below 's, shading is set to one; above 's but below 's, shading is two; and above 's, shading is three. First, we needed to determine how to assign the bits address bits of SRAM so as to store pixel information. There are two unused bits, indicating that our kb SRAM can store four images in all.
For the purposes of our paint application, we can toggle between two images using bit 17, controlled by the program. Bit 18 is left as a manual switch that the user can toggle to choose the half of memory that they want displayed or which two-image storage cluster, high or low.
Now that the algorithm is complete, the Java program requests the user to input a file path for analysis, and then asks the user for a path to write a collection of files containing a snippet of C source code to be included—holding an array declaration of byte values to be stored for part of the image.
Program memory offers a storage space of 65, bytes. For our x resolution displayed in a x frame , a still image occupies , bytes of memory. As such, we decided that it was best to write to SRAM a minimum of three times.
For simplicity and convenience, we have devised a scheme that writes to SRAM four separate times; each time, we write the values stored in an array of maximum length to 32, addresses in SRAM losing one pixel at the end, but avoiding visual incongruities by hiding the last column of each line when displayed on the screen so that a crisp line exists at the right-side of the image.
Bits 17 and 16 are held constant for each program execution. As such, the Java program outputs four files, each containing an array of length 32, where the value is the 8-bit RGBS value and the index represents the 15 least-significant address bits.
Accompanying the array is another variable, representing the two most-significant address bits for the partner array. The demand for a particular Vga To Component Video Converter is a good indication of its ability to perform the functions for which it was designed. If a product has been around for a while and still has a high demand, it is likely a good product.
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